1. Field of the Invention
The present invention relates to a drain voltage pumping circuit, and more particularly to a drain voltage pumping circuit to reduce current dissipation in program operation by detecting the number of bits for programming at the time of program operation on a flash memory cell and by allowing drain pumping voltage control depending on the number of cells for programming.
2. Description of the Prior Art
Generally, memory cells in a flash memory are by applying high voltage, for example, 8 through 9V to a control gate and the supply voltage, for example, 4 through 5V to a drain electrode. For supplying such high voltage or supply voltage, drain voltage pumping circuits are used.
FIG. 1 is a typical drain voltage pumping circuit. A drain voltage pumping unit 2 for programming memory cells in a memory cell array 1 comprises a ring oscillator 3 and a pumping unit 4.
Operation of a typical drain voltage circuit constituted as described above will be explained with reference to FIG. 2A and FIG. 2B.
FIG. 2A is a detailed circuit of the ring oscillator. The ring oscillator comprises: a NAND gate 5 to use enable signals En as input; a first delay unit 6 to delay output of the NAND gate 5; a first inverter I1 to inverse output of the first delay unit 6; a second delay unit 7 to delay output of the first inverter I1; a second inverter I2 to invent output of the second delay unit 7 and provide the output to a remain input terminal of the NAND gate 5; a third inverter I3 for generating a first control signal .phi.1 by inversing output of the second inverter I2; and a fourth inverter I4 for generating a second control signal .phi.2 by inversing output of the third inverter I3.
FIG. 2B is a detailed circuit of pumping unit. The pumping unit comprises: a first NMOS transistor and a second NMOS transistor N1 and N2 connected in parallel between the supply power Vcc and the first node K1; a first capacitor and a second capacitor C1 and C2 to use first and second control signals .phi.1 and .phi.2 of the ring oscillator as input; and a third NMOS transistor N3 connected between the first node K1 and the output terminal Out.
As described above, a typical drain voltage pumping circuit programmed 8 bits or 16 bits at the same time, using one pumping device, as shown in FIG. 2B.
For example, if a pumping circuit is constituted for programming when the number of bits for programming is assumed to be 16, excessive power dissipation occurs in programming 8 bits. Also, if a pumping circuit is constituted for programming when the number of bits for programming is assumed to be 8, enough program pumping output can not be obtained since current supply is small in 16 bits programming.